The present invention generally relates to semiconductor processing, and in particular to a method for improving a process for calibrating a photolithographic tool.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
FIGS. 1a and 1b illustrate problems associated with conventional polysilicon gate layer test wafers. FIG. 1a illustrates a reference wafer 10 having a pattern 15 formed thereon. The pattern 15 could include a plurality of fields, each field having an array of sub-fields and each sub-field having a number of component images formed thereon. FIG. 1b illustrates a portion of the reference wafer 10 including a silicon substrate layer 12, a dielectric or insulating layer 14 on the silicon substrate layer 12, and a first contact 16 and a second contact 18 on the insulating layer 14. The first contact 16 and the second contact 18 are made of a conductive material, such as polysilicon or metal. In a metrology measurement system, electron beams 20 are directed toward the reference wafer 10 and secondary electron emissions from the surface are detected by detectors (not shown). However, a charge 22 begins forming on the first contact 16 and the second contact 18 from the electron beams 20 due to the conductivity of the contacts. The charge build up 22 may cause deflection in the incident beam in addition to deflection and/or suppression of the secondary electron emissions.
In view of the above, an improvement of the calibration process is needed. In addition an improvement is needed in the structure and formation of the reference wafer.
The present invention provides for an improved method of making and using a reference wafer to calibrate metrology tools. Reference wafers are used in SEM to make precision and line width measurements repeatedly in order to maintain the tools in accordance with desired specifications. An electron beam may cause a charge buildup on an area of inspection pattern on the reference wafer if the elements and materials are not connected to a ground, as opposed to actual production wafers. This charge buildup may cause deflection of an incident electron beam and deflection and/or suppression of secondary electron emission resulting in erroneous secondary electron signals from the reference wafer.
The reference wafer of the present invention includes a silicon substrate, a dielectric or insulating layer disposed above the silicon substrate and a material (polysilicon, silicon nitride, metal, amorphous silicon) disposed above the insulating layer. The features (e.g., lines) are formed so that they extend through the insulating layer to the silicon substrate. The silicon substrate acts as a ground for the elements or materials forming the pattern (it is to be appreciated that an ion implantation may be performed to modify the electron dissipation properties of the base silicon to be more electron conductive). As a result, charge that is formed on the patterned layer due to charges induced by the electron beam dissipate into the silicon substrate thereby mitigating deleterious charge formation on the patterned layer.
In one aspect of the invention a reference wafer for calibrating a metrology tool set is provided. The reference wafer includes a substrate layer, an insulating layer formed over the substrate layer, a pattern formed over the insulating layer and at least one conductive path coupling at least a portion of the pattern to the substrate layer. The at least one conductive path provides a path to dissipate charge from the at least a portion of the pattern to the substrate layer.
In yet another aspect of the invention a method for calibrating a line width measurement metrology tool set over time is provided. The method includes the steps of using a reference wafer to calibrate the tool at a first time period, the reference wafer, including a substrate layer, an insulating layer formed over the substrate layer, a pattern formed over the insulating layer, and at least one conductive path coupling at least a portion of the pattern to the substrate layer, the at least one conductive path providing a path to dissipate charge from the at least a portion of the pattern to the substrate layer, and using the reference wafer to calibrate the tool at a second time period.
In another aspect of the invention a method for calibrating first and second metrology tool sets is provided. The method includes the steps of using a reference wafer to calibrate the first tool, the reference wafer, including a substrate layer, an insulating layer formed over the substrate layer, a pattern formed over the insulating layer, and at least one conductive path coupling at least a portion of the pattern to the substrate layer, the at least one conductive path providing a path to dissipate charge from the at least a portion of the pattern to the substrate layer and using the reference wafer to calibrate the second tool at a second time period.
One aspect of the invention relates to a SEM system. The system includes a line width measurement metrology tool set and a reference wafer adapted to be used to calibrate the tool. The reference wafer includes a silicon layer, an insulating layer above the silicon layer and at least one contact. The contact extends from the top of the silicon layer to above the top of the insulating layer. The system also includes a metrology system adapted to transmit an electron beam to the reference wafer and detect electron emissions based on characteristics of the reference wafer. The electron beam from the metrology system making contact with the at least one contact forms a charge on the at least one contact that dissipates through the silicon layer.
Another aspect of the present invention relates to a reference wafer for calibrating a line width measurement metrology tool set. The reference wafer includes a silicon layer, an insulating layer above the silicon layer and at least one contact. The contact extends from the top of the silicon layer to above the top of the insulating layer wherein an electron beam transmitted from a metrology system and making contact with the at least one contact forms a charge on the at least one contact that dissipates through the silicon layer.
Yet another aspect of the present invention provides for a method of fabricating a reference wafer. The method includes the steps of providing a substrate having an insulating layer, providing a photoresist layer over the insulating layer, developing the photoresist layer exposing portions of the insulating layer, etching the exposed portions of the insulating layer to form at least one via, stripping off the photoresist layer, filling the via with a conductive layer, the conductive layer covering the insulating layer, providing a second photoresist layer over the conductive layer, developing the second photoresist layer exposing portions of the conductive layer, etching the exposed portions of the insulating layer to form at least one contact and stripping off the second photoresist layer.
In yet another embodiment of the invention, a method for calibrating a line width measurement metrology tool set is provided. The method includes the steps of providing a reference wafer adapted to be used to calibrate the tool, the reference wafer having a silicon layer, an insulating layer above the silicon layer and at least one contact, the contact extending from the top of the silicon layer to above the top of the insulating layer, providing a metrology system adapted to transmit an electron beam to the reference wafer and detect secondary electron emissions based on characteristics of the reference wafer, wherein the electron beam transmitted from the metrology system and making contact with the at least one contact forms a charge on the at least one contact that dissipates through the silicon layer, providing a line width measurement metrology tool set coupled to the metrology system, transmitting an electron beam to the reference wafer from the metrology system and measuring the secondary electron emissions from the reference wafer and generating calibration data based on the characteristics of the reference wafer detected from the secondary electron emissions and adjusting the line width measurement metrology tool set based on the calibration data.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.